※※Recruitment New!※※Recruitment New!
Position: Physical Design – DFT/STA EngineerLocation: Tokyo – Yokohama
•Responsible for cutting edge DFT involving implementing key DFT logic modules, and verifying them.
•Working with the chip architecture team to define DFT specifications and define the chip test interface along with developing and implementing DFT architecture.
•Implementing DFT infrastructure and working with the validation team to verify DFT implementations and implement design changes.
•Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation).
•Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints.
•Take responsibility to develop Japanese customers on physical design business.
•Take responsibility to deal with customers to win new projects.
•5+ years experiences in physical design – DFT/STA.
•Familiarity with simulation, debugging tools, and working closely with design and verification team.
•Experience with multi-clock and multi-power domain designs. Familiarity with DFT insertion, and multi-mode timing constraints.
•Familiarity with hierarchical design approach, top-down design, timing and physical convergence.
•Experience with design synthesis and backend STA closure.
•Deep understanding of designs’ constraints development.
•Good understanding of AC timing from specs to implementation.
•Good understanding of DFT modes and their constraints.
•Able to setup full chip Level Timing Constraint.
•Programming in Perl, Tcl and C++ is a plus.
•N3+ Japanese certification will be a plus.
•Good at English communication.
•Ph.D/MS degree is not required, but preferred.
※BenefitsSalary: negotiableChance for career developmentProfessional working environmentOther allowances: transportation allowance, family allowance …etc